integrated circuit systems, inc. general description features ics9169c-27 block diagram frequency generator for pentium? based systems 9169c-27 rev c 04/16/98 pin configuration the ics9169c-27 is a low-cost frequency generator designed specifically for pentium based chip set systems. the integrated buffer minimizes skew and provides all the clocks required. a 14.318 mhz xtal oscillator provides the reference clock to generate standard pentium frequencies. the cpu clock makes gradual frequency transitions without violating the pll timing of internal microprocessor clock multipliers. twelve cpu clock outputs provide sufficient clocks for the cpu, chip set, memory and up to two dimm connectors (with four clocks to each dimm). either synchronous(cpu/2) or asynchronous (32 mhz) pci bus operation can be selected by latching data on the bsel input 32-pin soic/soj functionality 3.3v10%, 0-70 c crystal (x1, x2) = 14.31818 mhz pentium is a trademark on intel corporation. ? twelve selectable cpu clocks operate up to 83.3mhz ? maximum cpu jitter of 200ps ? six bus clocks support sync or async bus operation ? 250ps skew window for cpu outputs, 500ps skew window for bus outputs ? cpu clocks bus clocks skew 1-4ns (cpu early) ? integrated buffer outputs drive up to 30pf loads ? 3.0v - 3.7v supply range, cpu(1:6) outputs 2.5v(2.375- 2.62v) vdd option ? 32-pin soic/soj package ? logic inputs latched at power-on for frequency selection saving pins as input/output ? 48 mhz clock for usb support and 24 mhz clock for fd. address select cpu(1:12) (mhz) bus (1:6)mhz 48mhz 24mhz ref fs2 fs1 fs0 bsel=1 bsel=0 00 0 50 25 32 48 24 ref 00 1 60 30 32 48 24 ref 0 1 0 66.6 33.3 32 48 24 ref 0 1 1 ref/2 ref/4 ref/3 ref/2 ref/4 ref 1 0 0 55 27.5 32 48 24 ref 1 0 1 75 37.5 32 48 24 ref 1 1 0 83.3 41.7 32 48 24 ref 1 1 1 tristate tristate tristate tristate tristate tristate vdd groups: vdd = x1, x2, ref/bsel vddc1 = cpu1-6 vddc2 = cpu7-12 & pll core vddb = bus1-6 vddf = 48/24 mhz latched inputs: l1 = bsel l2 = fs0 l3 = fs1 l4 = fs2 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9169c-27 pin descriptions pin number pin name type description 1 vdd pwr power for device logic. 2x1 in xtal or external reference frequency input. this input includes xtal load capacitance and feedback bias for a 12-16mhz crystal, nominally 14.31818mhz. external crystal load of 30pf to gnd recommended for vdd power on faster than 2.0ms. 3 x2 out xtal output which includes xtal load capacitance. external crystal load of 10pf to gnd recommended for vdd power on faster than 2.0ms. 4,11,20,26 gnd pwr ground for device logic. 5 cpu(1) out processor clock output which is a multiple of the input reference frequency. fs0 in frequency multiplier select pins. see shared pin description.* 6,7,9,10,15,16,17,18,19 cpu (2:5) (8:12) out processor clock outputs which are a multiple of the input reference frequency. 8 vddc1 pwr power for cpu(1:6) output buffers only. can be reduced vdd for 2.5v (2.375-2.62v) next generation processor clocks. 12 cpu(6) out processor clock output which is a multiple of the input reference frequency internal pull up devices. fs1 in frequency multiplier select pin. see shared pin description.* 13 cpu(7) out processor clock output which is a multiple of the input reference frequency internal pull up devices. fs2 in frequency multiplier select pin. see shared pin description.* 14 vddc2 pwr power for cpu pll, logic and cpu(7:12)output buffers. must be nominal 3.3v (3.0 to 3.7v) 21,22,24,25,27,28 bus (6:1) out bus clock outputs which are a multiple of the input reference clock. 23 vddb pwr power for bus clock buffers bus(1:6). 29 vddf pwr power for fixed clock buffer (48 mhz, 24 mhz). 30 24mhz out fixed 24mhz clock (assuming a 14.31818mhz ref frequency). 31 48mhz out fixed 48mhz clock (assuming a 14.31818mhz ref frequency). 32 ref out fixed 14.31818mhz clock (assuming a 14.31818mhz ref frequency). bsel in selection for synchronous or asynchronous bus clock operation. see shared pin programming description late in this data sheet for further explanation.* * internal pull-up will vary from 350k to 500k based on temperature.
3 ics9169c-27 the ics9169c-27 includes a production test verification mode of operation. this requires that the fs0 and fs1 pins be programmed to a logic high and the fs2 pin be programmed to a logic low(see shared pin operation section). in this mode the device will output the following frequencies. note: ref is the frequency of either the crystal connected between the devices x1and x2 or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the device?s x1 pin. shared pin operation - input/output pins 5, 12, 13 and 32 on the ics9169c-27 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operation for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). shared pin operation - input/output pins test mode operation pin frequency ref ref 48mhz ref/2 24mhz ref/4 cpu (1:12) ref2 bus (1:6) bsel=1 ref/4 bsel = 0 ref/3 fig. 1 (resistors are surface mount devices shown schematically between 5.m. pads) *use only one programming resistor
4 ics9169c-27 fig. 2a fig. 2b fig. 3
5 ics9169c-27 technical pin function descriptions vdd this is the power supply to the internal logic of the device as well as the following clock output buffers: a. ref clock output buffers b. bus clock output buffers c. fixed clock output buffers this pin may be operated at any voltage between 3.0 and 5.5 volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the ac parameter table in this data sheet. gnd this is the power supply ground return pin for the internal logic of the device as well as the following clock output buffers: a. ref clock output buffers b. bus clock output buffers c. cpu clock output buffers d. fixed clock output buffers x1 this pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device? input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. x2 this pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. this pin also implements an internal crystal loading capacitor that is connected to ground. see the data tables for the value of the capacitor. cpu this pin is the clock output that drives processor and other cpu related circuitry that require clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by that which is applied to the vddc pins of the device. see note on vddc (1:2). see the functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. bus this pin is the clock output that is intended to drive the systems plug-in card bus. the voltage swing of these clocks is control-led by the supply that is applied to the vdd pin of the device. see the functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. fs0, fs1, fs2 these pins control the frequency of the clocks at the cpu, cpul, bus & sdram pins. see the funtionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. the device reads these pins at power-up and stores the programmed selection code in an internal data latch. (see programming section of this data sheet for configuration circuitry recommendations. bsel this pin controls whether the bus clocks will be synchronous (run at half the frequency) with the cpu and cpul clocks or whether they will be asynchronous (run at a pre-programmed fixed frequency) clock rate. it is a shared pin and is pro grammed the same way as the frequency select pins. vddc (1:2) these are the power supply pins for the cpu (1:6) and cpu (7:12) clock buffers. by separating the clock power pins, each group can receive the appropriate power decoupling and bypassing necessary to minimize emi and crosstalk between the individual signals. vddc1 can be reduced to 2.5v vdd for advanced processor clocks, which will bring cpu (1:6) outputs at 0 to 2.5v output swings. 48 mhz this is a fixed frequency clock that is typically used to drive super i/o peripheral device needs. 24 mhz this is a fixed frequency clock that is typically used to drive keyboard controller clock needs. ref this is a fixed frequency clock that runs at the same frequency as the input reference clock (typically 14.31818 mhz) is and typically used to drive video and isa bus requirements. vddb this power pin supplies the bus clock buffers. vddf this power pin supplies the 48/24 mhz clocks.
6 ics9169c-27 absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il - - 0.2v dd v input high voltage v ih 0.7v dd --v input low current i il v in = 0v -28.0 -10.5 - a input high current i ih v in = v dd -5.0 - 5.0 a output low current 1 i ol v ol = 0.8v; for cpu, bus, fixed clks 16.0 25.0 - ma output high current 1 i oh v ol = 2.0v; for cpu, bus, fixed clks --30.0-14.0 ma output low current 1 i ol v ol = 0.8v; for ref clk 19.0 30.0 - ma output high current 1 i oh v ol = 2.0v; for ref clk - -38 -16.0 ma output low voltage 1 v ol i ol = 8ma; for cpu, bus, fixed clks -0.30.4v output high voltage 1 v oh i oh = -8ma; for cpu, bus, fixed clks 2.4 2.8 - v output low voltage 1 v ol i ol = 10ma; for ref clk - 0.3 0.4 v output high voltage 1 v oh i oh = -15ma; for ref clk 2.4 2.8 - v supply current i dd @66.6 mhz; all outputs unloaded - 90 180 ma
7 ics9169c-27 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 t r1 20pf load, 0.8 to 2.0v cpu & bus -0.91.5ns fall time 1 t f1 20pf load, 2.0 to 0.8v cpu & bus - 0.8 1.4 ns rise time 1 t r2 20pf load, 20% to 80% cpu & bus -1.52.5ns fall time 1 t f2 20pf load, 80% to 20% cpu & bus - 1.4 2.4 ns duty cycle 1 d t 20pf load @ vout=1.4v 45 50 60 % jitter, one sigma 1 t j1s1 cpu & bus clocks; load=20pf, bsel=1 -50150 ps jitter, absolute 1 t jab1 cpu & bus clocks; load=20pf, bsel=1 -250 - 250 ps jitter, one sigma 1 t j1s2 ref & fixed clks; load=20pf - 1 3 % jitter, absolute 1 t jab2 ref & fixed clks; load=20pf -5 2 5 % input frequency 1 f i 12.0 14.318 16.0 mhz logic input capacitance 1 c in logic input pins - 5 - pf crystal oscillator capacitance 1 c inx x1, x2 pins - 18 - pf power-on time 1 t on from v dd =1.6v to 1st crossing of 66.6 mhz v dd supply ramp < 40ms -2.54.5 ms clock skew 1 t sk1 cpu to cpu; load=20pf; @1.4v - 150 250 ps clock skew 1 t sk2 bus to bus; load=20pf; @1.4v - 150 250 ps clock skew 1 t sk3 cpu to bus; load=20pf; @1.4v (cpu is early) 1 2.6 4 ns clock skew 1 t sk4 cpu (@3.3v) to cpu (@2.5v) (2.5v cpu is late) 0.5 1 ns
8 ics9169c-27 soic package ordering information ics9169cm-27 ics9169cj-27 pattern number (2 or 3 digit number for parts with rom code patterns) package type m=soic j=soj device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx m - ppp soj package 0.818 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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